1–30 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, December 2016 Altera Corporation
Volume 3
t
LOCK
(2)
— ——1——1——1——1—— 1 ms
Notes to Table 1–32:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX
devices.
(2) t
LOCK
is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices
(1),
(3)
(Part 2 of 2)
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices
(1),
(2),
(4)
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
f
HSCLK
(input
clock
frequency)
×10 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 5 — 132.5 MHz
×8 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 5 — 132.5 MHz
×7 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 5 — 132.5 MHz
×4 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 5 — 132.5 MHz
×2 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 5 — 132.5 MHz
×1 5 — 400 5 — 311 5 — 311 5 — 311 5 — 265 MHz
Device
operation in
Mbps
×10 100 — 400 100 — 311 100 — 311 100 — 311 100 — 265 Mbps
×8 80 — 400 80 — 311 80 — 311 80 — 311 80 — 265 Mbps
×7 70 — 400 70 — 311 70 — 311 70 — 311 70 — 265 Mbps
×4 40 — 400 40 — 311 40 — 311 40 — 311 40 — 265 Mbps
×2 20 — 400 20 — 311 20 — 311 20 — 311 20 — 265 Mbps
×1 10 — 400 10 — 311 10 — 311 10 — 311 10 — 265 Mbps
t
DUTY
— 45 — 55 45 — 55 45 — 55 45 — 55 45 — 55 %
TCCS — — — 200 — — 200 — — 200 — — 200 — — 200 ps
Output jitter
(peak to peak)
— — — 500 — — 500 — — 550 — — 600 — — 700 ps
t
RISE
20 – 80%,
C
LOAD
=
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
t
FALL
20 – 80%,
C
LOAD
=
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
t
LOCK
(3)
— ——1—— 1 —— 1 —— 1 —— 1 ms
Notes to Table 1–33:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at
the output pin of all I/O banks.
Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the
output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(3) t
LOCK
is the time required for the PLL to lock from the end-of-device configuration.
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
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