Altera Stratix - Page 199

Altera Corporation 5–19
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 1 of 2) Notes (1), (2)
Output Signal
All Stratix Devices EP1S30 to EP1S80 Devices Only
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
GCLK0
v
GCLK1
v
GCLK2
v
GCLK3
v
GCLK4
v
GCLK9
v
GCLK10
v
GCLK11
v
RCLK1
vv v
RCLK2
vv v
RCLK3
vv v
RCLK4
vv v
RCLK9
vv v
RCLK10
vv v
RCLK11
vv v
RCLK12
vv v
DIFFIOCLK1
v
DIFFIOCLK2
v
DIFFIOCLK3
v
DIFFIOCLK4
v
DIFFIOCLK5
v
DIFFIOCLK6
v
DIFFIOCLK7
v
DIFFIOCLK8
v
DIFFIOCLK9
v
DIFFIOCLK10
v
DIFFIOCLK11
v
DIFFIOCLK12
v
DIFFIOCLK13
v