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1–2 Altera Corporation

Stratix Device Handbook, Volume 2 July 2005

Introduction

Table 1–2. Stratix GX Device PLL Availability

Device

Fast PLLs Enhanced PLLs

1278561112

EP1S10C

vv vv

EP1S10D

vv vv

EP1S25C

vv vv

EP1S25D

vv vv

EP1S25F

vv vv

EP1S40D

vvvvvvvv

EP1S40G

vvvvvvvv

Table of Contents

Default Chapter3
- Table of Contents3
Chapter Revision Dates13
About this Handbook15
- How to Find Information15
- How to Contact Altera15
- Typographic Conventions16
Section I. Clock Management17
- Revision History17
- Introduction19
- Enhanced Plls23
- Fast Plls49
- Clocking57
- Board Layout68
- Conclusion74
Chapter 1. General-Purpose Plls in Stratix & Stratix GX Devices17
Section II. Memory75
- Revision History75
Chapter 2. Trimatrix Embedded Memory Blocks in Stratix & Stratix GX Devices77
- Introduction77
- Trimatrix Memory77
- Using Trimatrix Memory83
- Clock Modes92
- Designing with Trimatrix Memory99
- Read-During-Write Operation at the same Address101
  - Same-Port Read-During-Write Mode101
  - Mixed-Port Read-During-Write Mode102
- Conclusion103
Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices105
- Introduction105
- External Memory Standards105
- DDR Memory Support Overview114
- Conclusion131
Section III. I/O Standards133
- Revision History133
Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices133
- Introduction137
- Stratix & Stratix GX I/O Standards137
- High-Speed Interfaces151
- Stratix & Stratix GX I/O Banks153
- Hot Socketing163
  - DC Hot Socketing Specification164
  - AC Hot Socketing Specification164
- I/O Termination164
- I/O Pad Placement Guidelines166
- Power Source of Various I/O Standards174
- Conclusion178
- More Information178
- References178
Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices181
- Introduction181
- Stratix I/O Banks181
  - Stratix Differential I/O Standards182
  - Stratix Differential I/O Pin Location185
- Principles of SERDES Operation186
- Using SERDES to Implement DDR193
- Using SERDES to Implement SDR194
- Differential I/O Interface & Fast Plls196
- Receiver Data Realignment205
- Source-Synchronous Timing Budget210
- SERDES Bypass DDR Differential Signaling222
- High-Speed Interface Pin Locations225
- Differential I/O Termination226
- Board Design Consideration230
- Software Support231
- Summary255
Section IV. Digital Signal Processing (DSP)257
- Revision History257
Chapter 6. DSP Blocks in Stratix & Stratix GX Devices259
- Introduction259
- DSP Block Overview260
- Architecture263
- Operational Modes276
- Software Support286
- Conclusion286
Chapter 7. Implementing High Performance DSP Functions287
In Stratix & Stratix GX Devices287
- Introduction287
- Stratix & Stratix GX DSP Block Overview287
- Trimatrix Memory Overview290
- DSP Function Overview291
- Finite Impulse Response (FIR) Filters291
- Infinite Impulse Response (IIR) Filters320
- Matrix Manipulation331
  - Background on Matrix Manipulation331
  - Two-Dimensional Filtering & Video Imaging332
- Discrete Cosine Transform (DCT)338
  - DCT Background338
  - 2-D DCT Algorithm339
- Arithmetic Functions345
- Conclusion348
- References349
Section V. IP & Design Considerations351
- Revision History351
Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices353
- Introduction353
  - Related Links353
- 10-Gigabit Ethernet353
- Interfaces357
- I/O Characteristics for XSBI, XGMII & XAUI374
Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices379
- Introduction379
Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices393
- Introduction393
- General Architecture393
- Trimatrix Memory400
- DSP Block408
  - DSP Block Megafunctions408
- Plls & Clock Networks410
  - Clock Networks410
  - Plls411
- I/O Structure417
- Configuration422
- Conclusion424
Section VI. System Configuration & Upgrades425
- Revision History426
Chapter 11. Configuring Stratix & Stratix GX Devices427
- Introduction427
- Device Configuration Overview428
- Configuration File Size432
- Altera Configuration Devices433
- Configuration Schemes433
- Configuring Using the Microblaster Driver477
- Device Configuration Pins477
Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices487
- Introduction487
- Remote Configuration Operation487
  - Remote System Configuration Modes489
  - Remote System Configuration Components491
- Quartus II Software Support498
  - Altremote_Update Megafunction500
  - Remote Update WYSIWYG ATOM503
- Using Enhanced Configuration Devices505
  - Local Update Programming File Generation507
  - Remote Update Programming File Generation518
- Combining MAX Devices & Flash Memory528
- Using an External Processor529
- Conclusion530
Section VII. PCB Layout Guidelines531
- Revision History531
Chapter 13. Package Information for Stratix Devices533
- Introduction533
- Device & Package Cross Reference533
- Thermal Resistance534
- Package Outlines535
Chapter 14. Designing with 1.5-V Devices549
- Introduction549
- Power Sequencing & Hot Socketing549
- Using Multivolt I/O Pins550
- Voltage Regulators551
- V Regulator Application Examples567
  - Synchronous Switching Regulator Example568
- Board Layout569
  - Split-Plane Method571
- Conclusion571
- References572

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