Altera Stratix - Page 221

Altera Corporation 5–41
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–27. Differential High-Speed Timing Diagram & Timing Budget
RSKM
TUI
Time Unit Interval (TUI)
RSKM
TCCS
TPPos (min)
Bit
n
Internal
Clock
Falling Edge
t
SW
(min)
Bit
n
t
SW
(max)
Bit
n
TPPos (max)
Bit
n
RSKM
TCCS
T
SWBEGIN
T
SWEND
Sampling
Window
TCCS
2
Receiver
Input Data
Transmitter
Output Data
Internal
Clock
Synchronization
External
Clock
Receiver
Input Clock
Internal
Clock
External
Input Clock
Timing Budget
Timing Diagram
Clock Placement
Sampling
Window (SW)
RSKM
TCCS
TPPos (min)
Bit
n + 1
TPPos (max)
Bit
n + 1