Altera Stratix - Page 285

Altera Corporation 6–27
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Figure 6–15. Input Shift Registers Configured for a FIR Filter
CLRN
D
Q
ENA
Data A
Data B
A[n] × B[n] (to adder)
CLRN
D Q
ENA
CLRN
D
Q
ENA
CLRN
D
Q
ENA
Data A
Data B
A[n - 1] × B[n - 1] (to adder)
CLRN
D
Q
ENA
CLRN
D Q
ENA
CLRN
D
Q
ENA
Data A
Data B
A[n - 2] × B[n - 2] (to adder)
CLRN
D
Q
ENA
CLRN
D
Q
ENA