13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.2 Data communications using auto refresh
13 - 23
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM
OVERVIEW
11
MULTIPLE CPU SYSTEM
CONFIGURATION
12
CONCEPT OF MULTIPLE
CPU SYSTEM
13
COMMUNICATIONS
BETWEEN CPU
MODULES
14
PARAMETERS ADDED
FOR MULTIPLE CPU
SYSTEMS
15
STARTING A MULTIPLE
CPU SYSTEM
16
TROUBLESHOOTING
1) CPU No.1 stores send data in D0 to D9.
2) CPU No.1 turns on the data set completion bit (M0).
• In the END processing of CPU No.1, the above data are written to the auto
refresh area in its CPU No.1 send area.
• The auto refresh area data in the CPU No.1 send area are sent to CPU
No.2.
By the user program of CPU No.2, data are read from the CPU No.1 auto refresh
area to the internal buffer.
3) CPU No.2 detects ON of the data set completion bit (M0).
4) CPU No.2 processes the received data.
5) CPU No.2 turns on the data processing completion bit (this information is
refreshed to M32 of CPU No.1.)
In the END processing of CPU No.1, the data are read from the auto refresh area
in its CPU No.2 send area to the specified device.
6) CPU No.1 detects ON of the data processing completion bit (M32), and turns
off the data set completion bit (M0).
By the user program of CPU No.2, check that the data set completion bit (M0) of
CPU No.1 is OFF.
7) CPU No.2 detects OFF of the data set completion bit (M0).
8) CPU No.2 turns off the data processing completion bit (this information is
refreshed to M32 of CPU No.1.)
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