Mitsubishi Electric Q12DCCPU-V - Control CPU Settings (Required); Multiple CPU Synchronous Startup Setting (Optional); Multiple CPU High Speed Transmission Area Setting (Required)

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14.1 Parameter List
14.1.6 Control CPU settings (required)
14
PARAMETERS ADDED FOR MULTIPLE CPU
SYSTEMS
14.1.6 Control CPU settings (required)
Specify a control CPU for each of I/O modules and intelligent function modules that are
mounted on a base unit in the multiple CPU system.
CPU No.1 is set for all by default.
14.1.7 Multiple CPU synchronous startup setting (optional)
In the multiple CPU system, synchronized startup is available for the selected CPU
modules. ( Page 13-48, Section 13.9)
14.1.8 Multiple CPU high speed transmission area setting (required)
The settings can be configured for the data communications using the multiple CPU
transmission areas in CPU shared memories (using auto refresh). ( Page 13-24,
Section 13.3.3)
Figure 14.3 Control CPU setting
Q12DCCPU-V
Q06CCPU-V
Q06CCPU-V-B
Control CPU setting
Q12DCCPU-V
Q06CCPU-V
Q06CCPU-V-B
Q12DCCPU-V
Q06CCPU-V
Q06CCPU-V-B