Mitsubishi Electric Q12DCCPU-V - Transmission Delay Time; Assurance of Data Sent Among Cpus

13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.3 Communication using the multiple CPU high speed transmission area and auto refresh
13 - 29
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM OVERVIEW
11
MULTIPLE CPU SYSTEM CONFIGURATION
12
CONCEPT OF MULTIPLE CPU SYSTEM
13
COMMUNICATIONS BETWEEN CPU MODULES
14
PARAMETERS ADDED FOR MULTIPLE CPU SYSTEMS
15
STARTING A MULTIPLE CPU SYSTEM
16
TROUBLESHOOTING
(3) Precautions
(a) Transmission delay time
A transmission delay caused by auto refresh will be within the following range.
0.09 ms to (1.80 + (Sending-side write time
*1
+ Receiving-side reading cycle
*2
2)) ms
* 1 For the write time of the QBF_ToBuf function, refer to the following.
Appendix 1
* 2 When the receiving side is a C Controller module, there is no reading cycle (0ms).
When the receiving side is other than a C Controller module, it is the scan time on the receiving
side.
(b) Assurance of data sent among CPUs
Depending on the timing of sending data from the host CPU and auto-refreshing
data in another CPU, new and old data may be mixed in the area for each CPU
(data separation).
The following is how to avoid such data separation in communications using auto
refresh.
1) Preventing 32-bit data from being fragmented
Data are sent in units of 32 bits in auto refresh.
Since auto refresh settings are configured in units of 32 bits, 32-bit data are not
fragmented.
2) Preventing more than 32-bit data from being fragmented
In the auto refresh method, data are sent in order of decreasing transfer
numbers set as the auto refresh setting parameters.
Assigning a transfer number smaller than actual transfer numbers to an
interlock device.
An interlock program example is shown in (3) (c) in this section below.
(c) Interlock program example
Figure 13.21 is an interlock program example for sending data from CPU No.1
(programmable controller CPU) to CPU No.2 (C Controller module).
The parameter setting in Table 13.13 uses the following interlock devices.
• M0 as an interlock device (Data set completion bit) of CPU No.1
• M32 as an interlock device (Data processing completion bit) of CPU No.2
Table 13.13 Parameter setting example for interlock program
Auto refresh setting for CPU No.1
Direction
Auto refresh setting for CPU No.2
CPU
No.
Transfer
No.
CPU specific send
range
Device
setting
CPU
No.
Transfer
No.
CPU specific send
range
Points Start End Start End Points Start End
CPU
No.1
Transfer 1 2 0 1 M0 M31
CPU
No.1
Transfer 1 2 0 1
Transfer 2 10 2 11 D0 D9 Transfer 2 10 2 11
CPU
No.2
Transfer 1 2 0 1 M32 M63
CPU
No.2
Transfer 1 2 0 1