Moog MSD Servo Drive Series

The parameters for the EnDat interface are described in Section "EnDat
(cyclical)X7" on page 58, as are the differences in using the EnDat interface with the
“cyclical” method and “one-time reading” method.
NOTE
 SpecialTTLencoderswithcommutationtrackscanberunon
encoderchannelCh3(X8)bysettingP 507[0] - ENC_CH3_Selto
TTL_COM(5).
6.7.6SSI(cyclical)X8
Ch3: SSI(2) - Cyclical SSI
The software versions required to run the SSI encoder interface are the standard
software versions for the MSD Servo Drive and MSDSingle-Axis Servo Drive
Compact.
NOTE

Pleasenote thelimitations thatapply whenrunningEnDatand
SSI encoders (see Section "Limiting for EnDat and SSI" on
page50).
SSI (Synchronous Serial Interface) is a digital encoder interface that is supported by
a large number of manufacturers. It is not standardized, meaning that manufacturers
are free to support the interface as they like. The pseudo-standard described below
has however been established for motor feedback interfaces. Moog supports this
version first and foremost.
The following table lists the parameters for cyclical SSI operation on encoder
channel Ch3. It also points out possible differences between the use of the SSI
interface with the “cyclical” method and “one-time reading” method when using
Sin/Cos encoders with an SSI absolute value interface.
MOOG
ID
No.: CB40859-001 Date: 02/2018
MSD Servo Drive- Device Help
85
6 Encoder
SSI encoder basics and requirements
The SSI interface on the MSD Servo Drive has been designed as an actual motor
feedback interface. Accordingly, the connected SSI encoder must meet the following
criteria:
 Clockanddatainactivelevel=HIGH
 Thecurrentpositionmustbeinternallystoredatthefirstfallingclockedge
 Nolengthenedcalculationtime(infirstcycle)
 Withthefirstrisingclockedge,theencodermustshiftthedatatothefirst
positionbittobetransmitted(MSB)
 1Mbpsrate
 Datacoding=BinaryorGray
 Readingdataafterthedatabitsendispermissible
 125µscycle(i.e.internalpositionrefreshrate≪125µs)
 Monofloptime≥6µs
 Datalinesdrivenwithlogic0duringmonofloptime
 Noparitybit
 Noerrorbitsorotherstatusbits
 ≤14MultiTurnbits