R&S FSL TRACe Subsystem (1xEV-DO, K84)
1300.2519.12 6.667 E-11
Value Description Range Unit
<RHO1> RHOoverall–1 over all slots over all chips with
start of averaging at the half–slot limit
<RHO2> RHOoverall–2 over all slots over all chips with
start of averaging at the quarter–slot limit
<PPILot> Absolute power in the PILOT channel type dBm
<PMAC> Absolute power in the MAC channel type dBm
<PDATa> Absolute power in the DATA channel type dBm
<PPReamble> Absolute power in the PREAMBLE channel
type
dBm
<MACCuracy> Composit EVM in % %
<DMTYpe> Modulation type in the DATA channel type:
2 = QPSK, 3 = 8–PSK, 4 = 16–QAM
MACTive Number of active
<MACTive> Number of active MAC channels
<DACTive> Number of active DATA channels
<PLENGth> Length of preamble in chips
<RHO> RHO value for the selected channel type/slot
<PCDerror> Peak Code Domain error in dB dB
<IQIMbalance> IQ imbalance in % %
<IQOFfset> IQ offset in % %
<SRATe> Symbol rate in ksps ksps
<CHANnel> Channel number
<SFACtor> Spreading factor of the channel
<TOFFset> If the evaluation of the timing and phase offset
is not active(refer to CDPower:TPMeas) or
more than 50 active channels are in the signal,
the value 9 is returned. For inactive channels,
the value 9 is returned.
s
<POFFset> If the evaluation of the timing and phase offset
is not active (refer to CDPower:TPMeas) or
more than 50 active channels are in the signal,
the value 9 is returned. For inactive channels,
the value 9 is returned.
<CDPRelative> relative level of the channel referenced to total
power in the channel type
{–
...
}
dB
<CDPAbsolute> absolute level of the code channel at the
selected channel slot
{–
...
}
dBm
<EVMRms> Error vector magnitude rms in % %
<EVMPeak> Error vector magnitude peak in % %
<MTYPe> Modulation type:
0 = BPSK–I, 1 = BPSK–Q, 2 = QPSK, 3 = 8–
PSK, 4 = 16–QAM, 5 = 2BPSK (if complex
analysis selected for PILOT, PREAMBLE or
MAC)
Power vs Chip
The command returns one value for every chip in the following order:
<level value in dBm>, <level value in dBm>, …
The number of results that are displayed is always 2048, one power level for every chip.
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