Status Reporting System R&S FSL
1300.2519.12 5.14 E-11
Status Reporting System
T
he status reporting system (refer to Fig. 5–4) stores all information on the present operating state of
the instrument, and on errors which have occurred. This information is stored in the status registers and
in the error queue. The status registers and the error queue can be queried via GPIB or via the Ethernet.
The information is of a hierarchical structure. The register status byte (STB) defined in IEEE 488.2 and
its associated mask register service request enable (SRE) form the uppermost level. The STB receives
its information from the standard event status register (ESR) which is also defined in IEEE 488.2 with
the associated mask register standard event status enable (ESE) and registers STATus:OPERation and
STATus:QUEStionable which are defined by SCPI and contain detailed information on the instrument.
The IST flag ("Individual STatus") and the parallel poll enable register (PPE) allocated to it are also part
of the status reporting system. The IST flag, like the SRQ, combines the entire instrument status in a
single bit. The PPE fulfills the same function for the IST flag as the SRE for the service request.
The output buffer contains the messages the instrument returns to the controller. It is not part of the
status reporting system but determines the value of the MAV bit in the STB.
Structure of an SCPI Status Register
Each standard SCPI register consists of 5 parts which each have a width of 16 bits and have different
functions (refer to Fig. 5–3). The individual bits are independent of each other, i.e. each hardware status
is assigned a bit number that applies to all five parts. For example, bit 3 of the STATus:OPERation
register is assigned to the hardware status "wait for trigger" in all five parts. Bit 15 (the most significant
bit) is set to zero for all parts. Thus the contents of the register parts can be processed by the controller
as positive integer.
15 14 13 12 PTRansition part 3 2 1 0
15 14 13 12 EVENt part 3 2 1 0
15 14 13 12 ENABle part 3 2 1 0
& & & & & & & & & & & & & & & &
to higher-order register
Sum bit
& = logical AN
= logical OR
of all bits
+
+
15 14 13 12 NTRansition part 3 2 1 0
15 14 13 12 CONDition part 3 2 1 0
Fig. 5–3 The status–register model
CONDition part
The CONDition part is directly written into by the hardware or the sum bit of the next lower register. Its
contents reflects the current instrument status. This register part can only be read, but not written into or
cleared. Its contents is not affected by reading.
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