Rohde & Schwarz R&S FSL3 - Status:questionable:acplimit Register

Status Reporting System R&S FSL
1300.2519.12 5.20 E-11
Bit No. Meaning
8
CALibration
The bit is set if a measurement is performed unaligned (label UNCAL)
9
LIMit (device–specific)
This bit is set if a limit value is violated (see also section "STATus:QUEStionable:LIMit
Register")
10
LMARgin (device–specific)
This bit is set if a margin is violated (see also section "STATus:QUEStionable:LMARgin
Register")
11
SYNC (device–dependent)
This bit is set if, in measurements or pre–measurements, synchronization to midamble
fails or no burst is found.
This bit is also set if, in pre–measurements mode, the result differs too strongly from the
expected value (see also "STATus:QUEStionable:SYNC Register").
12
ACPLimit (device–specific)
This bit is set if a limit for the adjacent channel power measurement is violated (see also
section "STATus:QUEStionable:ACPLimit Register")
13 to 14 Not used
15 This bit is always 0.
STATus:QUEStionable:ACPLimit Register
This register contains information about the observance of limits during adjacent power measurements.
It can be read using the commands 'STATus:QUEStionable:ACPLimit :CONDition?' and
'STATus:QUEStionable:ACPLimit[:EVENt]?'
Table 5–7 Meaning of bits in STATus:QUEStionable:ACPLimit register
Bit No.
Meaning
0
ADJ UPPer FAIL
This bit is set if the limit is exceeded in the upper adjacent channel
1
ADJ LOWer FAIL
This bit is set if the limit is exceeded in the lower adjacent channel.
2
ALT1 UPPer FAIL
This bit is set if the limit is exceeded in the upper 1st alternate channel.
3
ALT1 LOWer FAIL
This bit is set if the limit is exceeded in the lower 1st alternate channel.
4
ALT2 UPPer FAIL
This bit is set if the limit is exceeded in the upper 2nd alternate channel.