Rohde & Schwarz R&S FSL3 - Status:questionable:power Register

R&S FSL Status Reporting System
1300.2519.12 5.23 E-11
Bit No.
Meaning
2
LMARgin 3 FAIL
This bit is set if limit margin 3 is violated.
3
LMARgin 4 FAIL
This bit is set if limit margin 4 is violated.
4
LMARgin 5 FAIL
This bit is set if limit margin 5 is violated.
5
LMARgin 6 FAIL
This bit is set if limit margin 1 is violated.
6
LMARgin 7 FAIL
This bit is set if limit margin 7 is violated.
7
LMARgin 8 FAIL
This bit is set if limit margin 8 is violated.
8 to 14 Not used
15 This bit is always 0.
STATus:QUEStionable:POWer Register
This register contains all information about possible overloads of the unit.
It can be read using the commands STATus:QUEStionable:POWer:CONDition? and STATus
:QUEStionable:POWer[:EVENt]?.
Table 5–11 Meaning of bits in STATus:QUEStionable:POWer register
Bit No.
Meaning
0
OVERload
This bit is set if the RF input is overloaded. OVLD is displayed.
1
UNDerload
This bit is set if the RF input is underloaded. UNLD is displayed.
2
IF_OVerload
This bit is set if the IF path is overloaded. IFOVL is displayed.
3 to 14 Not used
15 This bit is always 0.