Rohde & Schwarz R&S FSL3 - Status:questionable:limit Register; Status:questionable:lmargin Register

Status Reporting System R&S FSL
1300.2519.12 5.22 E-11
STATus:QUEStionable:LIMit Register
This register contains information about the observance of limit lines. It can be read using the
commands STATus:QUEStionable:LIMit:CONDition? and
STATus:QUEStionable:LIMit[:EVENt]?.
Table 5–9 Meaning of bits in STATus:QUEStionable:LIMit register
Bit No.
Meaning
0
LIMit 1 FAIL
This bit is set if limit line 1 is violated.
1
LIMit 2 FAIL
This bit is set if limit line 2 is violated.
2
LIMit 3 FAIL
This bit is set if limit line 3 is violated.
3
LIMit 4 FAIL
This bit is set if limit line 4 is violated.
4
LIMit 5 FAIL
This bit is set if limit line 5 is violated.
5
LIMit 6 FAIL
This bit is set if limit line 6 is violated.
6
LIMit 7 FAIL
This bit is set if limit line 7 is violated.
7
LIMit 8 FAIL
This bit is set if limit line 8 is violated.
8 to 14 Not used
15 This bit is always 0.
STATus:QUEStionable:LMARgin Register
This register contains information about the observance of limit margins. It can be read using the
commands STATus:QUEStionable:LMARgin:CONDition? and STATus
:QUEStionable:LMARgin[:EVENt]?.
Table 5–10 Meaning of bits in STATus:QUEStionable:LMARgin register
Bit No.
Meaning
0
LMARgin 1 FAIL
This bit is set if limit margin 1 is violated.
1
LMARgin 2 FAIL
This bit is set if limit margin 2 is violated.