Rohde & Schwarz R&S FSL3 - Page 751

WLAN TX Measurements (K91K91n) – Status Reporting System R&S FSL
1300.2519.12 5.42 E-11
STATus:QUEStionable:LIMit Register
This register comprises information about the observance of limit lines in the corresponding
measurement window (LIMit 1 corresponds to screen A, LIMit 2 to screen B). It can be queried with the
STATus:QUEStionable:LIMit<1|2>:CONDition? and
STATus:QUEStionable:LIMit<1|2>[:EVENt]? commands.
Note: No limit lines are displayed in screen A and therefore all bits in the LIMit1 register will always be
set to 0.
Bit No Meaning
0 to 1 These bits are not used.
2
LIMit FAIL
This bit is set if the ETSI Spectrum Mask limit line is violated.
3
LIMit FAIL
This bit is set if the Spectrum Flatness (Upper) limit line is violated.
4
LIMit FAIL
This bit is set if the Spectrum Flatness (Lower) limit line is violated.
5
LIMit FAIL
This bit is set if the IEEE Spectrum Mask limit line is violated.
6
LIMit FAIL
This bit is set if the PVT Rising Edge max limit is violated.
7
LIMit FAIL
This bit is set if the PVT Rising Edge mean limit is violated.
8
LIMit FAIL
This bit is set if the PVT Falling Edge max limit is violated.
9
LIMit FAIL
This bit is set if the PVT Falling Edge mean limit is violated.
10 to 14 These bits are not used.
15 This bit is always 0.