Altera Stratix - Page 130

3–26 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Overview
Figure 3–14. DQ Captures with Non-Inverted & Inverted Shifted DQS
DQ at the pin
DQS shifted
by 90˚
Output of register A
1
(dataout_h)
Output of latch C
1
(dataout_l)
Output of register B
1
DQS inverted and
shifted by 90˚
Output of register A
1
(dataout_h)
Output of latch C
1
(dataout_l)
Output of register B
1
DQS at the pin
Shifted DQS Signal is Not Inverted
Shifted DQS Signal is Inverted
DQ & DQS Signals
D
n − 1
D
n − 2
D
n − 2
D
n − 2
D
n − 1
D
n
D
n
D
n − 3
D
n − 1
D
n − 1
D
n