Altera Stratix - Page 129

Altera Corporation 3–25
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
The Stratix and Stratix GX DDR IOE structure requires you to invert the
incoming DQS signal by using a NOT gate to ensure proper data transfer.
The altdq megafunction automatically adds the inverter when it
generates the DQ signals. As shown in Figure 3–10, the inclock signal's
rising edge clocks the A
I
register, inclock signal's falling edge clocks
the B
I
register, and latch C
I
is opened when inclock is one. In a DDR
memory read operation, the last data coincides with DQS being low. If
you do not invert the DQS pin, you do not get this last data because the
latch does not open until the next rising edge of the DQS signal. The NOT
gate is inserted automatically if the altdg megafunction is used;
otherwise you need to add the NOT gate manually.
Figure 3–14 shows waveforms of the circuit shown in Figure 3–12. The
second set of waveforms in Figure 3–14 shows what happens if the
shifted DQS signal is not inverted; the last data, D
n
, does not get latched
into the logic array as DQS goes to tristate after the read postamble time.
The third set of waveforms in Figure 3–14 shows a proper read operation
with the DQS signal inverted after the 90° shift; the last data D
n
does get
latched. In this case the outputs of register A
I
and latch C
I
, which
correspond to dataout_h and dataout_l ports, are now switched
because of the DQS inversion.