Altera Stratix - Page 127

Altera Corporation 3–23
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE Note (1)
Notes to Figure 3–12:
(1) You can use the altdq megafunction to generate the DQ signals.
(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register A
OE
during compilation.
(3) The outclock signal is phase shifted –90° from the system clock.
(4) The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq
megafunction to generate the DQ signals.
DQ
DFF
DQ
LATCH
ENA
DQ
DFF
Input Register A
I
Input Register B
I
Latch C
DQ
DFF
DQ
DFF
0
1
DQ
DFF
TRI
DQ Pin
OE Register A
OE
Output Register A
O
Output Register B
O
Logic Array
Latch
dataout_l
dataout_h
outclock
(3)
datain_h
datain_l
OE
inclock (from DQS bus)
neg_reg_out
I
(4)
(2)