Section I–2 Altera Corporation
Clock Management Stratix Device Handbook, Volume 2
1 November 2003, v2.2 ● Updated the “Lock Detect” section.
October 2003, v2.1
● Updated the “VCCG & GNDG” section.
● Updated Figure 1–14.
July 2003, v2.0
● Updated clock multiplication and division, spread spectrum, and Notes 1
and 8 in Table 1-3.
● Updated inclk[1..0] port name in Table 1-4.
● Updated ranges for EPLL post-scale and pre-scale dividers on page 1-9
● Added 1.8V HSTL support for EPLL in Table 1-6 and 1-13.
● New requirement to assert are set signal each PLL when it has to re-
acquire lock on either a new clock after loss of lock (page 1-16)
● Corrected input port extswitch to clkswitch throughout this
chapter.
● Updated clkloss description in Table 1-9.
● Updated text on jitter for spread spectrum on page 1-38.
● Removed PLL specifications. See Chapter 4 of Volume 1.
Chapter Date/Version Changes Made
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