5–68 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Stratix devices, you can align the input data with respect to the
tx_inclock port and align the output data with respect to the
tx_outclock port. The MegaWizard Plug-In Manager uses the
alignment of input and output data to automatically calculate the phase
for the fast PLL outputs. Both of these parameters default to
EDGE_ALIGNED, and other values are CENTER_ALIGNED, 45_DEGREES,
135_DEGREES, 180_DEGREES, 225_DEGREES, 270_DEGREES, and
315_DEGREES. CENTER_ALIGNED is the same as 180 degrees aligned
and is required for the HyperTransport technology I/O standard.
Clock Frequency & Clock Period
The fields in the Specify the input clock rate by box specify either the
frequency or the period of the input clock going into the fast PLL.
However, you cannot specify both. If your design uses the same input
clock to feed a transmitter and a receiver module simultaneously, the
Quartus II software can merge the fast PLLs for both the transmitter and
receiver when the Use common PLLs for Tx & Rx option is turned on.
Page 4 of the altlvds_tx MegaWizard Plug-In Manager
This section describes the parameters found on page 4 of the
altlvds_tx MegaWizard Plug-In Manager (see Figure 5–43).
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