6–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
Input Registers
Each operand feeds an input register or the multiplier directly. The DSP
block has the following signals (one of each controls every input and
output register):
■ clock[3..0]
■ ena[3..0]
■ aclr[3..0]
The input registers feed the multiplier and drive two dedicated shift
output lines, shiftouta and shiftoutb. The shift outputs from one
multiplier block directly feed the adjacent multiplier block in the same
DSP block (or the next DSP block), as shown in Figure 6–4 on page 6–7, to
form a shift register chain. This chain can terminate in any block, i.e., you
can create any length of shift register chain up to 224 registers. A shift
register is useful in DSP applications such as FIR filters. When
implementing 9 × 9 and 18 × 18 multipliers, you do not need external
logic to create the shift register chain because the input shift registers are
internal to the DSP block. This implementation greatly reduces the
required LE count and routing resources, and produces repeatable
timing.
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