Altera Stratix - Page 289

Altera Corporation 7–3
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
The DSP blocks are organized into columns enabling efficient horizontal
communication with adjacent TriMatrix memory blocks. Tables 7–1 and
7–2 show the DSP block resources in Stratix and Stratix GX devices,
respectively.
Table 7–1. DSP Block Resources in Stratix Devices
Device DSP Blocks
Maximum 9
× 9
Multipliers
Maximum 18 × 18
Multipliers
Maximum 36 × 36
Multipliers
EP1S10 6 48 24 6
EP1S20 10 80 40 10
EP1S25 10 80 40 10
EP1S30 12 96 48 12
EP1S40 14 112 56 14
EP1S60 18 144 72 18
EP1S80 22 176 88 22
Table 7–2. DSP Block Resources in Stratix GX Devices
Device DSP Blocks
Maximum 9
× 9
Multipliers
Maximum 18 × 18
Multipliers
Maximum 36 × 36
Multipliers
EP1SGX10C 6 48 24 6
EP1SGX10D 6 48 24 6
EP1SGX25C 10 80 40 10
EP1SGX25D 10 80 40 10
EP1SGX25F 10 80 40 10
EP1SGX40D 14 112 56 14
EP1SGX40G 14 112 56 14