Altera Stratix - Page 336

7–50 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Matrix Manipulation
Figure 7–29. Implementation of 3 × 3 Convolutional Filter Block
DSP Block in Four-Multipliers Adder Mode (9-bit)
LE implemented
adder
DSP Block in Sim
p
le Multi
p
lier Mode
(
8-bit
)
w
9
x(m + 1, n + 1)
w
8
x(m + 1, n )
w
7
x(m + 1, n - 1)
w
6
x(m , n + 1)
w
5
x(m , n )
w
4
x(m , n - 1)
w
3
x(m - 1, n + 1)
w
2
x(m - 1, n )
w
1
x(m - 1, n - 1)
y(m
, n )
Note: Unused multipliers and
adders grayed out. These
multipliers can be used by other
functions.