Altera Stratix - Page 7

Altera Corporation vii
Contents Contents
High-Speed Phase Adjust ............................................................................................................. 5–21
Counter Circuitry ........................................................................................................................... 5–22
Fast PLL SERDES Channel Support ............................................................................................ 5–23
Advanced Clear & Enable Control .............................................................................................. 5–25
Receiver Data Realignment ................................................................................................................ 5–25
Data Realignment Principles of Operation ................................................................................. 5–25
Generating the TXLOADEN Signal ............................................................................................. 5–27
Realignment Implementation ....................................................................................................... 5–28
Source-Synchronous Timing Budget ................................................................................................ 5–30
Differential Data Orientation ........................................................................................................ 5–30
Differential I/O Bit Position ......................................................................................................... 5–31
Timing Definition ........................................................................................................................... 5–32
Input Timing Waveform ............................................................................................................... 5–39
Output Timing ................................................................................................................................ 5–40
Receiver Skew Margin ................................................................................................................... 5–40
Switching Characteristics .............................................................................................................. 5–42
Timing Analysis .............................................................................................................................. 5–42
SERDES Bypass DDR Differential Signaling ................................................................................... 5–42
SERDES Bypass DDR Differential Interface Review ................................................................. 5–42
SERDES Clock Domains ................................................................................................................ 5–42
SERDES Bypass DDR Differential Signaling Receiver Operation .......................................... 5–43
SERDES Bypass DDR Differential Signaling Transmitter Operation ..................................... 5–44
High-Speed Interface Pin Locations ................................................................................................. 5–45
Differential I/O Termination ............................................................................................................. 5–46
R
D
Differential Termination .......................................................................................................... 5–46
HyperTransport & LVPECL Differential Termination ............................................................. 5–47
PCML Differential Termination ...................................................................................................5–47
Differential HSTL Termination .................................................................................................... 5–48
Differential SSTL-2 Termination .................................................................................................. 5–49
Board Design Consideration .............................................................................................................. 5–50
Software Support ................................................................................................................................. 5–51
Differential Pins in Stratix ............................................................................................................. 5–51
Fast PLLs .......................................................................................................................................... 5–52
LVDS Receiver Block ..................................................................................................................... 5–60
LVDS Transmitter Module ........................................................................................................... 5–65
SERDES Bypass Mode ................................................................................................................... 5–70
Summary ............................................................................................................................................... 5–75
Section IV. Digital Signal Processing (DSP)
Revision History .................................................................................................................... Section IV–1
Chapter 6. DSP Blocks in Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 6–1
DSP Block Overview ............................................................................................................................. 6–2
Architecture ............................................................................................................................................ 6–5