Altera Stratix - Page 85

Altera Corporation 2–9
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
TriMatrix memory supports mixed-width configurations, allowing
different read and write port widths. When using mixed-width mode, the
LSB is written to or read from first. For example, take a RAM that is set up
in mixed-width mode with write data width ×8 and read data width ×2.
If a binary 00000001 is written to write dress 0, the following is read out
of the ×2 output side:
Tables 2–7 to 2–9 show the mixed width configurations for the M512,
M4K, and M-RAM blocks, respectively.
Read Address ×2 data
00 01(LSB of ×8 data)
01 00
10 00
11 00(MSB of ×8 data)
Table 2–7. M512 Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port
Write Port
512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 64 × 9 32 × 18
512 × 1
vvvvv
256 × 2
vvvvv
128 × 4
vvv v
64 × 8
vv v
32 × 16
vvv v
64 × 9
v
32 × 18
v
Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Read Port
Write Port
4K × 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1
vvv v v v
2K × 2
vvv v v v
1K × 4
vvv v v v
512 × 8
vvv v v v
256
× 16
vvv v v v