Mitsubishi Electric Q12DCCPU-V - Page 431

13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.4 Data communications without using auto refresh
13 - 33
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM OVERVIEW
11
MULTIPLE CPU SYSTEM CONFIGURATION
12
CONCEPT OF MULTIPLE CPU SYSTEM
13
COMMUNICATIONS BETWEEN CPU MODULES
14
PARAMETERS ADDED FOR MULTIPLE CPU SYSTEMS
15
STARTING A MULTIPLE CPU SYSTEM
16
TROUBLESHOOTING
<Interlock program example>
Depending on the following timing, old and new data for each CPU may be mixed
(data separation).
• Writing data to the user setting area in another CPU and reading another
CPU's user setting area data from the host CPU
• Writing data to the user setting area in the host CPU and reading host CPU's
user setting area data from another CPU
The following explains how to avoid data separation in data communications
through user setting areas.
Figure 13.23 shows an example, in which an interlock is programmed for sending
data from CPU No.1 (programmable controller CPU) to CPU No.2 (C Controller
module) using user setting areas in the multiple CPU high speed transmission
areas.
Sending side program for CPU No.1 (programmable
controller CPU)
Receiving side program for CPU No.2 (C Controller module)
{
:
unsigned short usBuf; /* Data storage destination */
unsigned short pusData[128]; /* Data storage destination */
:
/****************************************************************/
/* The ON status of CPU No.1 data set completion bit is detected.*/
/****************************************************************/
while(1){
sRet = QBF_FromBuf(lPath, 0x3E0, 10010, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
if( (usBuf & 0x1) == 0x1 ) break; /* When 1 is set, processing gets out from the loop. */
taskDelay(2);
}
/****************************************************************/
/* Data are read out from the CPU No.1 user setting area. */
/****************************************************************/
sRet = QBF_FromBuf(lPath, 0x3E0, 10000, 10, pusData, 128);
if( sRet != 0) return(sRet);
/*****************************************************************/
/* CPU No.2 data processing completion bit turns ON. */
/*****************************************************************/
usBuf = 1;
sRet = QBF_ToBuf(lPath, 0x3E1, 10000, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
/*****************************************************************/
/* The OFF status of CPU No.1 data set completion bit is detected.*/
/*****************************************************************/
while(1){
sRet = QBF_FromBuf(lPath, 0x3E0, 10010, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
if( (usBuf & 0x1) == 0x0 ) break; /* When 0 is set, processing gets out from the loop. */
taskDelay(2);
}
/*****************************************************************/
/* CPU No.2 data processing completion bit turns OFF. */
/*****************************************************************/
usBuf = 0;
sRet = QBF_ToBuf(lPath, 0x3E1, 10000, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
}
Figure 13.23 Interlock program example
1)
2)
6)
M0
Write
command
U3E0\ U3E1\
G10010.0 G10000.0
U3E0\ U3E1\
U3E0\
SET G10010.0
U3E0\
RST G10010.0
RST M0
G10010.0 G10000.0
Set send data in
user setting area
(U3E0\ G10000 to G10009).
3)
4)
5)
7)
8)