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NXP Semiconductors LPC11U3x User Manual

NXP Semiconductors LPC11U3x
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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 236 of 523
NXP Semiconductors
UM10462
Chapter 11: LPC11U3x/2x/1x USB2.0 device controller
Remark: When receiving a SETUP token for endpoint zero, the HW will only read the
SETUP bytes Buffer Address offset to know where it has to store the received SETUP
bytes. The hardware will ignore all other fields. In case the SETUP stage contains more
than 8 bytes, it will only write the first 8 bytes to memory. A USB compliant host must
never send more than 8 bytes during the SETUP stage.
For EP0 transfers, the hardware will do auto handshake as long as the ACTIVE bit is set
in EP0_IN/OUT command list. Unlike other endpoints, the hardware will not clear the
ACTIVE bit after transfer is done. Thus, the software should manually clear the bit
whenever it receives new setup packet and set it only after it has queued the data for
control transfer. See Figure 23 “
Flowchart of control endpoint 0 - OUT direction.
T RW Endpoint Type
0: Generic endpoint. The endpoint is configured as a bulk or interrupt
endpoint
1: Isochronous endpoint
NBytes RW For OUT endpoints this is the number of bytes that can be received in this
buffer.
For IN endpoints this is the number of bytes that must be transmitted.
HW decrements this value with the packet size every time when a packet is
successfully transferred.
Note: If a short packet is received on an OUT endpoint, the active bit will be
cleared and the NBytes value indicates the remaining buffer space that is
not used. Software calculates the received number of bytes by subtracting
the remaining NBytes from the programmed value.
Address
Offset
RW Bits 21 to 6 of the buffer start address.
The address offset is updated by hardware after each successful
reception/transmission of a packet. Hardware increments the original value
with the integer value when the packet size is divided by 64.
Examples:
If an isochronous packet of 200 bytes is successfully received, the
address offset is incremented by 3.
If a packet of 64 bytes is successfully received, the address offset is
incremented by 1.
If a packet of less than 64 bytes is received, the address offset is not
incremented.
Table 227. Endpoint commands
Symbol Access Description

Table of Contents

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NXP Semiconductors LPC11U3x Specifications

General IconGeneral
BrandNXP Semiconductors
ModelLPC11U3x
CategoryMicrocontrollers
LanguageEnglish

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