Panasonic FP Series - Page 1281

Appendix Programming Information
1280
No. Name Default Values
403 Pulse catch input:
X101
Disable Disable/Enable
403 Pulse catch input:
X102
Disable Disable/Enable
403 Pulse catch input:
X200
Disable Disable/Enable
403 Pulse catch input:
X201
Disable Disable/Enable
403 Pulse catch input:
X202
Disable Disable/Enable
404/
405
Interrupt input:
X0
Interrupt 0
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X1
Interrupt 1
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X2
Interrupt 2
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X3
Interrupt 3
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X4
Interrupt 4
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X5
Interrupt 5
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X6
Interrupt 6
Unused Rising edge/Falling edge
404/
405
Interrupt input:
X7
Interrupt 7
Unused Rising edge/Falling edge
404/
406
Interrupt input
X100
Interrupt 8
Unused Rising edge/Falling edge
404/
406
Interrupt input
X101
Interrupt 9
Unused Rising edge/Falling edge
404/
406
Interrupt input
X102
Interrupt 10
Unused Rising edge/Falling edge
404/
406
Interrupt input
X200
Interrupt 11
Unused Rising edge/Falling edge
404/
406
Interrupt input
X201
Interrupt 12
Unused Rising edge/Falling edge
404/
406
Interrupt input
X202
Interrupt 13
Unused Rising edge/Falling edge
If the same input has been set as high-speed counter input, pulse catch input or
interrupt input, the following order of precedence is effective: High-speed
counter  Pulse catch  Interrupt.
The two-phase input mode requires a second channel. If channels 0, 2, 4, or 6
have been set to two-phase mode, channels 1, 3, 5, or 7, respectively, must also
be set to this mode.
The settings for pulse catch inputs and interrupt inputs can only be specified in
the system registers.