Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 129
UG366 (v2.5) January 17, 2011
FPGA TX Interface
When the 8B/10B encoder is bypassed and the TX_DATA_WIDTH is 10, 20, or 40, the
TXCHARDISPMODE and TXCHARDISPVAL ports are used to extend the TXDATA port
from 8 to 10 bits, 16 to 20 bits, or 32 to 40 bits. Table 3-2 shows the data transmitted when
the 8B/10B encoder is disabled.
TXUSRCLK and TXUSRCLK2 Generation
The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTX transmitter. The required rate
for TXUSRCLK depends on the internal datapath width of the GTXE1 primitive and the TX
line rate of the GTX transmitter. Equation 3-1 shows how to calculate the required rate for
TXUSRCLK.
Equation 3-1
TXUSRCLK can be generated internally to the GTX transceiver. This functionality is
controlled by the GEN_TXUSRCLK attribute. Table 3-3 describes the situations in which
the TXUSRCLK can be generated internally by the GTX transceiver. In these cases, the
TXUSRCLK port must be tied Low.
TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTX
transceiver. Most signals into the TX side of the GTX transceiver are sampled on the
positive edge of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a fixed-rate relationship
based on the TX_DATA_WIDTH setting. Table 3-4 shows the relationship between
TXUSRCLK2 and TXUSRCLK per TX_DATA_WIDTH values.
Table 3-2: TX Data Transmitted when 8B/10B Encoder Bypassed
< < Data transmission order is right to left < <
Data
Transmitted
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
TXCHARDISPMODE[3]
TXCHARDIPSVAL[3]
TXDATA[31:24]
TXCHARDISPMODE[2]
TXCHARDIPSVAL[2]
TXDATA[23:16]
TXCHARDISPMODE[1]
TXCHARDIPSVAL[1]
TXDATA[15:8]
TXCHARDISPMODE[0]
TXCHARDIPSVAL[0]
TXDATA[7:0]
Table 3-3: TXUSRCLK Internal Generation Configurations
TX_DATA_WIDTH GTX Lanes in Channel
(1)
GEN_TXUSRCLK
1-Byte 8, 10
1TRUE
2 or more FALSE
2-Byte 16, 20 1 or more TRUE
4-Byte 32, 40 1 or more FALSE
Notes:
1. For single lane protocols such as 1 Gb/s Ethernet, “GTX Lanes in Channel” is 1. For multiple lane
protocols like XAUI, “GTX Lanes in Channel” is 2 or more.
TXUSRCLK Rate
Line Rate
Internal Datapath Width
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English