Xilinx Virtex-6 FPGA User Manual

268 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
After Connecting RXN/RXP
When the RX data to the GTX transceiver comes from a connector that can be plugged in
and unplugged, the RX CDR must be reset when the data source is plugged in to ensure
that it can lock to incoming data. When the guidelines in Link Idle Reset Support, page 264
are followed, the electrical idle reset situation is automatically managed.
After an RX Elastic Buffer Error
After an RX elastic buffer overflow or underflow, the RX elastic buffer must be reset using
the RXBUFRESET port to ensure correct behavior.
Before Channel Bonding
For successful channel bonding, the RX elastic buffers of all the bonded transceivers must
be written using the same recovered frequency, and read using the same RXUSRCLK
frequency.
To provide RXUSRCLK of the same frequency to all bonded transceivers, a low-skew clock
buffer (for example, a BUFG) must be used to drive all the RXUSRCLK ports from the same
clock source. Bonding should not be attempted until the clock source is stable.
To provide the same recovered clock to all bonded transceivers:
• All TX data sources must be locked to the same reference clock.
• All bonded transceivers must have CDR lock to the incoming data.
The required reset for channel bonding is:
• To automatically reset the CDR of all bonded transceivers, set
RX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR, and
RX_EN_IDLE_HOLD_CDR to TRUE.
• Wait for CDR lock and bit alignment on all bonded transceivers.
• Either assert RXBUFRESET to all bonded transceivers or, for an automatic reset, set
RX_EN_IDLE_RESET_BUF = TRUE to enable the RXBUFRESET sequence.
• Attempt channel bonding.
See RX CDR, page 204 for recommendations on how to detect CDR lock.
After Changing Channel Bonding Mode on the Fly
When set to TRUE, RX_EN_MODE_RESET_BUF enables automatic reset of the RX elastic
buffer when the RXCHANBONDMASTER, RXCHANBONDSLAVE, or
RXCHANBONDLEVEL ports change. See RX Channel Bonding, page 247.
After a PRBS Error
PRBSCNTRESET is asserted to reset the PRBS error counter.
After an Oversampler Error
If RXOVERSAMPLEERR goes High to indicate an overflow or underflow in the
oversampling block FIFO, asserting RXRESET clears it.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English