Xilinx Virtex-6 FPGA User Manual

254 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Setting Channel Bonding Sequences
The channel bonding sequence is programmed in the same way as the clock correction
sequence. CHAN_BOND_SEQ_LEN sets the length of the sequence, and
CHAN_BOND_SEQ_1_* sets the values of the sequence. If CHAN_BOND_SEQ_2_USE is
TRUE, CHAN_BOND_SEQ_2_* sets the values for the alternate second sequence.
The number of active bits in each subsequence depends on RX_DATA_WIDTH and
RX_DECODE_SEQ_MATCH (see RX Clock Correction, page 240). Figure 4-42 shows how
the subsequence bits are mapped.
As with clock correction sequences, channel bonding sequences can have don't care
subsequences. CHAN_BOND_SEQ_1_ENABLE and CHAN_BOND_SEQ_2_ENABLE set
these bytes. Figure 4-43 shows the mapping of the enable attributes for the channel
bonding subsequences.
Setting the Maximum Skew
When the master receives a channel bonding sequence, it does not trigger channel bonding
immediately. Several more bytes must arrive in case the slaves have more latency. This
wait time effectively becomes the maximum skew that the RX elastic buffer can handle. If
the skew is greater than this wait time, the slaves might not receive the sequence by the
time the master triggers channel bonding (see Figure 4-44).
Figure 4-44 shows two FIFOs, one for the master and one for the slave. If the slave is
behind the master, the master must wait several cycles before triggering channel bonding,
otherwise the slow slave does not have the channel bonding sequence in its buffer.
X-Ref Target - Figure 4-42
Figure 4-42: Channel Bonding Sequence Settings
X-Ref Target - Figure 4-43
Figure 4-43: Channel Bonding Sequence Mapping
8-Bit Channel Bonding Sequence
1 = Sequence is a K Character
0 = Sequence is Regular Character
1 = Sequence Uses Inverted Disparity
0 = Sequence Uses Regular Disparity
7:0
UG366_c4_39_051509
89CHAN BOND_SEQ_x_y
UG366_c4_40_051509
3412
CHAN_BOND_SEQ_x_4 CHAN_BOND_SEQ_x_3 CHAN_BOND_SEQ_x_2
CHAN_BOND_SEQ_x_ENABLE
CHAN_BOND_SEQ_x_1
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English