Xilinx Virtex-6 FPGA User Manual

140 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
Notes relevant to Figure 3-11:
1. GTXTEST[1] is only required when the TX output clock divider,
TXPLL_DIVSEL_OUT, is set to /2 or /4.
2. The timing of the reset sequencer inside the GTX TX depends on the frequency of an
internal clock and certain configuration attributes. The estimate given in Figure 3-11
assumes that the frequency of the internal clock is 50 MHz with default values for the
configuration attributes.
3. The entire GTX TX is affected by GTXTXRESET. If the RX PLL is supplying the clock
for the TX datapath, GTXTXRESET and GTXRXRESET must be tied together.
GTX TX Component-Level Resets
GTX TX component resets are primarily used for special cases. These resets are needed
when only the reset of a specific subsection is required. Each of the component-level reset
signals is described in Table 4-52, page 261.
All transmitter component resets are asynchronous. Table 3-9 summarizes the transmitter
resets and the components that they reset.
Table 3-9: Available Transmitter Resets and the Components Reset by Them
Component
Configuration
GTXTXRESET
TXPLLPOWERDOWN (Falling Edge)
PLLTXRESET
TXRESET
TXDLYALIGNRESET
TX PCS
FPGA TX Interface ✓✓✓ ✓
TX Gearbox ✓✓✓ ✓
TX Buffer ✓✓✓ ✓
8B/10B Encoder ✓✓✓ ✓
TX Polarity ✓✓✓ ✓
Pattern Generator ✓✓✓ ✓
5x Oversampler ✓✓✓ ✓
TX Delay Aligner ✓✓
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English