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Xilinx Virtex-6 FPGA User Manual

Xilinx Virtex-6 FPGA
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222 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Ports and Attributes
Table 4-34 defines the RX comma alignment and detection ports.
Table 4-34: RX Comma Alignment and Detection Ports
Port Dir Clock Domain Description
RXBYTEISALIGNED Out RXUSRCLK2 This signal from the comma detection and realignment circuit is
High to indicate that the parallel data stream is properly aligned
on byte boundaries according to comma detection.
0: Parallel data stream not aligned to byte boundaries
1: Parallel data stream aligned to byte boundaries
There are several cycles after RXBYTEISALIGNED is asserted
before aligned data is available at the FPGA RX interface.
RXBYTEISALIGNED responds to plus comma alignment when
PCOMMA_
DETECT is TRUE. RXBYTEISALIGNED responds
to minus comma alignment when MCOMMA_
DETECT is
TRUE.
RXBYTEREALIGN Out RXUSRCLK2 This signal from the comma detection and realignment circuit
indicates that the byte alignment within the serial data stream
has changed due to comma detection.
0: Byte alignment has not changed
1: Byte alignment has changed
Data can be lost when alignment occurs, which can cause data
errors (and disparity errors when the 8B/10B decoder is used).
RXCOMMADET Out RXUSRCLK2 This signal is asserted when the comma alignment block detects
a comma. The assertion occurs several cycles before the comma
is available at the FPGA RX interface.
0: Comma not detected
1: Comma detected
RXCOMMADETUSE In RXUSRCLK2 RXCOMMADETUSE activates the comma detection and
alignment circuit.
0: Bypass the circuit
1: Use the comma detection and alignment circuit
Bypassing the comma and alignment circuit reduces RX
datapath latency.
RXENMCOMMAALIGN In RXUSRCLK2 Aligns the byte boundary when comma minus is detected.
0: Disabled
1: Enabled
RXENPCOMMAALIGN In RXUSRCLK2 Aligns the byte boundary when comma plus is detected.
0: Disabled
1: Enabled
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Xilinx Virtex-6 FPGA Specifications

General IconGeneral
BrandXilinx
ModelVirtex-6 FPGA
CategoryTransceiver
LanguageEnglish

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