Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 221
UG366 (v2.5) January 17, 2011
RX Byte and Word Alignment
X-Ref Target - Figure 4-27
Figure 4-27: Manual Data Alignment Using RXSLIDE for RX_DATA_WIDTH = 20 Bits
RXUSRCLK2
RXSLIDE
RXDATA
TXDATA
Slide Results on RXDATA
After Several Cycles of Latency
00000000000000010000
00000000000000010000 00000000000000100000 00000000000001000000
UG366_c4_27_103010
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