Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 17
UG366 (v2.5) January 17, 2011
Preface
About This Guide
This document shows how to use the GTX transceivers in Virtex®-6 FPGAs. In this
document:
• Virtex-6 FPGA GTX transceiver is abbreviated as GTX transceiver.
• GTXE1 is the name of the instantiation primitive that instantiates one Virtex-6 FPGA
GTX transceiver.
•A Quad or Q is a cluster or set of four GTX transceivers that share two differential
reference clock pin pairs and analog supply pins.
Guide Contents
This manual contains the following chapters:
• Chapter 1, Transceiver and Tool Overview
• Chapter 2, Shared Transceiver Features
• Chapter 3, Transmitter
• Chapter 4, Receiver
• Chapter 5, Board Design Guidelines
• Appendix A, 8B/10B Valid Characters
• Appendix B, DRP Address Map of the GTX Transceiver
• Appendix C, Low Latency Design
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/
products/virtex6.
• Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
• Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
www.BDTIC.com/XILINX

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English