Xilinx Virtex-6 FPGA User Manual

192 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
RX Out-of-Band Signaling
Functional Description
The GTX receiver provides support for decoding the Out-of-Band (OOB) sequences
described in the Serial ATA (SATA) and Serial Attach SCSI (SAS) specifications and
supports beaconing described in the PCI Express specification. GTX receiver support for
SATA/SAS OOB signaling consists of the analog circuitry required to decode the OOB
signal state and state machines to decode bursts of OOB signals for SATA/SAS COM
sequences.
The GTX receiver also supports beacons that are PCI Express compliant by using interface
signals defined in the PHY Interface for the PCI Express (PIPE) Specification. The FPGA logic
decodes the beacon sequence.
Ports and Attributes
Table 4-9 defines the RX OOB ports.
Table 4-9: RX OOB Ports
Port Direction Clock Domain Description
COMINITDET Out RXUSRCLK2 Indicates detection of a COMINIT sequence.
COMSASDET Out RXUSRCLK2 Indicates detection of a COMSAS sequence.
COMWAKEDET Out RXUSRCLK2 Indicates detection of a COMWAKE sequence.
GATERXELECIDLE In Async Optional port. This port is tied to zero for PCIe and SATA
modes (default). For other usages, this port is asserted High to
gate the RXELECIDLE output (see Figure 4-8).
IGNORESIGDET In Async Optional port. This port is tied to zero for PCIe and SATA
modes (default). For other usages, this port is asserted High to
disable RX signal electrical idle detection logic from resetting
other GTX transceivers logic, including comma detection, RX
elastic buffer logic, and DFE logic (see Figure 4-8). When
IGNORESIGDET is set High, it prevents the following
attributes from automatically triggering an internal reset or
hold on RX electrical idle:
• RX_EN_IDLE_RESET_BUF
• RX_EN_IDLE_HOLD_CDR
• RX_EN_IDLE_RESET_FR
• RX_EN_IDLE_RESET_PH
• RX_EN_IDLE_HOLD_DFE
RXELECIDLE Out Async Indicates the differential voltage between RXN and RXP
dropped below the minimum threshold
(OOBDETECT_THRESHOLD). Signals below this threshold are
OOB signals.
1: OOB signal detected. The differential voltage is below the
minimum threshold.
0: OOB signal not detected. The differential voltage is above
the minimum threshold.
This port is intended for PCI Express and SATA standards.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English