Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 285
UG366 (v2.5) January 17, 2011
Power Supply and Filtering
There are potentially two major disadvantages to linear regulators: minimum dropout
voltage and limited efficiency. Linear regulators require an input voltage that is higher
than the output voltage. This minimum dropout voltage often depends on the load
current. Even low dropout linear regulators require a minimum difference between the
input voltage and the output voltage of the regulator. The system power supply design
must consider the minimum dropout voltage requirements of the linear regulators.
The efficiency of a linear regulator depends on the voltage difference between the input
and output of the linear regulator. For instance, if the input voltage of the regulator is
2.5 V
DC
and the output voltage of the regulator is 1.2 V
DC
, the voltage difference is
1.3 V
DC
. Assuming that the current into the regulator is essentially equal to the current out
of the regulator, the maximum efficiency of the regulator is 48%. Thus for every watt
delivered to the load, the system must consume an additional watt for regulation. This
power consumed by the regulator generates heat that must be dissipated by the system.
Providing a means to dissipate the heat generated by the linear regulator can drive up the
system cost. So even though from a simple component count and complexity cost the
linear regulator appears to have an advantage over the switching regulator, if the overall
system cost is considered including power consumption and heat dissipation, the linear
regulator can be at a disadvantage in high current applications.
Switching Regulator
A switching regulator can provide a very efficient means to deliver a well-regulated
voltage for the GTX analog power supply. Unlike the linear regulator, the switching
regulator does not depend on the voltage drop between the input voltage of the regulator
and the output voltage to provide regulation. Therefore the switching regulator can supply
large amounts of current to the load while maintaining high power efficiency. It is not
uncommon for a switching regulator to maintain efficiencies of 95% or greater. This
efficiency is not severely impacted by the voltage drop between the input of the regulator
and the output, and it is impacted by the load current in a much lesser degree than the
linear regulator. Because of the efficiency of the switching regulator, the system does not
need to supply as much power to the circuit, and it does not need to provide a means to
dissipate power consumed by the regulator.
The disadvantages to the switching regulator are complexity of the circuit and noise
generated by the regulator switching function. Switching regulator circuits are usually
more complex than linear regulator circuits. This shortcoming in switching regulators has
recently been addressed by several switching regulator component vendors. Normally, a
switching power supply regulation circuit requires a switching transistor element, an
inductor, and a capacitor. Depending on the required efficiency and load requirements, a
switching regulator circuit might require external switching transistors and inductors.
Besides the component count, these switching regulators require very careful placement
and routing on the PCB to be effective.
Switching regulators generate significant noise and therefore usually require additional
filtering before the voltage is delivered to the GTX analog power supply input of the
Virtex-6 FPGA. The amplitude of the noise should be limited to less than 10 mV
PK-PK
.
Therefore the power supply filter should be designed to attenuate the noise from the
switching regulator so that it meets this requirement.
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Xilinx Virtex-6 FPGA Specifications

General

Technology	40nm
Clock Data Recovery (CDR)	Integrated
Logic Cells	Up to 760, 000
I/O Pins	Up to 1200
Transceiver Features	Pre-emphasis, equalization
Transceiver Protocol Support	PCIe, SATA, Ethernet, CPRI, OBSAI, Serial RapidIO
Power Consumption	Varies by model and configuration
Transceiver Type	Multi-Gigabit Transceivers (RocketIO GTP/GTX)

Summary

Preface: About This Guide

Guide Contents

Lists the chapters and appendices included in this manual.

Additional Documentation

Provides links to other Xilinx documents for further information.

Chapter 1: Transceiver and Tool Overview

Overview

Introduces the Virtex-6 FPGA GTX transceiver and its features.

Port and Attribute Summary

Summarizes GTX ports and attributes, grouped by functionality.

Simulation

Explains prerequisites and setup for simulating GTX transceiver designs.

Implementation

Details mapping GTX transceivers to device resources and UCF creation.

Chapter 2: Shared Transceiver Features

Reference Clock Input Structure

Describes the structure and ports for reference clock inputs.

Reference Clock Selection

Explains how to select and route reference clocks for GTX transceivers.

PLL

Details the Phase-Locked Loop (PLL) architecture and its settings.

Power Down

Describes the various power-down modes and capabilities of the GTX transceiver.

Loopback

Explains loopback modes for testing the transceiver datapath.

ACJTAG

Covers the ACJTAG interface support for GTX transceivers.

Dynamic Reconfiguration Port

Explains the DRP for dynamic parameter changes in GTXE1 primitive.

Chapter 3: Transmitter

TX Overview

Introduces the functional blocks and key elements of the GTX transmitter.

FPGA TX Interface

Describes the gateway for transmitting data to the GTX transceiver.

TX Initialization

Details the procedures for resetting and initializing the GTX TX.

TX 8B/10B Encoder

Explains the 8B/10B encoding scheme used for outgoing data.

TX Gearbox

Describes support for 64B/66B and 64B/67B encoding for high-speed protocols.

TX Buffer

Explains the TX buffer's role in resolving phase differences between domains.

TX Buffer Bypass

Covers the advanced feature of bypassing the TX buffer for reduced latency.

TX Pattern Generator

Details the PRBS and other patterns for testing signal integrity.

TX Oversampling

Explains the built-in 5X oversampling feature for serial rates.

TX Polarity Control

Describes the function to invert outgoing data polarity before transmission.

TX Fabric Clock Output Control

Details the serial and parallel clock divider control for TX fabric clocks.

TX Configurable Driver

Explains the high-speed current-mode differential output buffer features.

TX Receiver Detect Support for PCI Express Designs

Describes the feature for detecting receiver presence on a link.

TX Out-of-Band Signaling

Covers support for SATA/SAS OOB sequences and PCI Express beaconing.

Chapter 4: Receiver

RX Overview

Introduces the functional blocks and key elements of the GTX receiver.

RX Analog Front End

Describes the high-speed current-mode input differential buffer.

RX Out-of-Band Signaling

Covers support for decoding SATA/SAS OOB sequences and PCI Express beacons.

RX Equalizer

Explains the circuit for compensating high-frequency losses in the channel.

RX CDR

Details the Clock Data Recovery circuit for extracting clock and data.

RX Fabric Clock Output Control

Covers serial and parallel clock divider control for RX fabric clocks.

RX Margin Analysis

Discusses methods for determining link quality via eye diagrams.

RX Polarity Control

Describes the function to invert incoming data polarity.

RX Oversampling

Explains the built-in 5X oversampling for low serial rates.

RX Pattern Checker

Details the built-in PRBS checker for testing channel signal integrity.

RX Byte and Word Alignment

Explains the process of aligning serial data to byte boundaries.

RX Loss-of-Sync State Machine

Describes the state machine for detecting channel malfunction.

RX 8B/10B Decoder

Explains the decoder for RX data, indicating errors and control sequences.

RX Buffer Bypass

Covers the advanced feature of bypassing the RX elastic buffer for low latency.

RX Elastic Buffer

Explains the buffer for resolving clock domain differences.

RX Clock Correction

Details the circuit for tolerating frequency differences between clock domains.

RX Channel Bonding

Describes using the RX elastic buffer to cancel skew between lanes.

RX Gearbox

Describes support for 64B/66B and 64B/67B encoding for high-speed protocols.

RX Initialization

Details the procedures for resetting and initializing the GTX RX.

FPGA RX Interface

Describes the interface for receiving RX data from the GTX RX.

Chapter 5: Board Design Guidelines

Overview

Discusses implementing GTX transceivers on a PCB for optimal performance.

Pin Description and Design Guidelines

Describes GTX transceiver pins and provides design guidelines.

Termination Resistor Calibration Circuit

Explains the circuit for calibrating termination resistors.

Analog Power Supply Pins

Details the MGTAVCC and MGTAVTT analog power supply pins.

Reference Clock

Focuses on the selection criteria for reference clock sources.

Power Supply Distribution Network

Discusses issues regarding power supply implementation on the PCB.

Crosstalk

Explains how crosstalk degrades GTX transceiver performance and how to avoid it.

SelectIO Usage Guidelines

Provides guidelines for SelectIO interface usage to minimize GTX impact.