Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 149
UG366 (v2.5) January 17, 2011
TX Gearbox
External Sequence Counter Operating Mode
As shown in Figure 3-14, the external sequence counter operating mode uses the
TXSEQUENCE[6:0], TXDATA[31:0], and TXHEADER[2:0] inputs. A binary counter must
exist in the user logic to drive the TXSEQUENCE input port. For 64B/66B encoding, the
counter increments from 0 to 32 and repeats from 0. For 64B/67B encoding, the counter
increments from 0 to 66 and repeats from 0. When using 64B/66B encoding, tie
TXSEQUENCE[6] to a logic 0 and tie the unused TXHEADER[2] to a logic 0. The sequence
counter increment ranges ({0 to 32}, {0 to 66}) are identical for both the 2-byte and 4-byte
interfaces. However, the counter must increment once every two TXUSRCLK2 cycles when
using a 2-byte interface and every TXUSRCLK2 cycle when using a 4-byte interface.
Due to the nature of the 64B/66B and 64B/67B encoding schemes, user data is held
(paused) during various sequence counter values. Data is then paused for two
TXUSRCLK2 cycles in 2-byte mode and for one TXUSRCLK2 cycle in 4-byte mode. Valid
data transfer is resumed on the next TXUSRCLK2 cycle. The data pause only applies to
TXDATA and not to TXHEADER.
• 64B/67B encoding: data is held (paused) for sequence counter values of 21, 44, and 65.
• 64B/66B encoding, data is held (paused) at counter value 31.
Figure 3-15 shows how a pause occurs at counter value 31 when using a 4-byte interface,
external sequence counter mode, and 64B/66B encoding.
X-Ref Target - Figure 3-14
Figure 3-14: TX Gearbox in External Sequence Counter Mode
Data Source
Pause
Sequence Counter
0-32 or 0-66
TXSEQUENCE[6:0]
TXHEADER[2:0]
TXDATA[15:0] or TXDATA[31:0]
TX Gearbox
(in GTX Transceiver)
Design in FPGA Logic
UG366_c3_04_051509
X-Ref Target - Figure 3-15
Figure 3-15: Pause at Sequence Counter Value 31
TXUSRCLK20
1
24 25 26 27 28 29 30 31 320 1
1
2
2
3 456
-
-
TXHEADER0
TXSEQUENCE0
TXDATA0
UG366_c3_05_051509
c1a9308dd38921414e658bf853365af5523cd4135714e976
Pause for 1 USRCLK2 cycle. Data is ignored.
120459d5
4e1fea877c5804988777acf1e38287118d14111a629a147087964daa
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English