Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 269
UG366 (v2.5) January 17, 2011
FPGA RX Interface
After Comma Realignment
When set to TRUE, RX_EN_REALIGN_RESET_BUF enables automatic reset of the RX
elastic buffer during comma realignment.
FPGA RX Interface
Functional Description
The FPGA receives RX data from the GTX RX through the FPGA RX interface. Data is read
from the RXDATA port on the positive edge of RXUSRCLK2. RXDATA can be configured
to be one, two, or four bytes wide. The actual width of the port depends on the
RX_DATA_WIDTH attribute and RXDEC8B10BUSE port settings. Port widths can be 8, 10,
16, 20, 32, and 40 bits.
The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the RX line
rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled. In
some operating modes, a second parallel clock (RXUSRCLK) must be provided for the
internal PCS logic in the receiver. This section shows how to drive the parallel clocks and
explains the constraints on those clocks for correct operation. The highest receiver data
rates require a 4-byte interface to achieve an RXUSRCLK2 rate in the specified operating
range.
Interface Width Configuration
The Virtex-6 FPGA GTX transceiver contains an internal 2-byte datapath. The FPGA
interface width is configurable by setting the RX_DATA_WIDTH attribute. When the
8B/10B decoder is enabled, the FPGA interface must be configured to 10, 20, or 40 bits.
When the 8B/10B decoder is bypassed, the FPGA interface is configured to any of the
available widths: 8, 10, 16, 20, 32, and 40 bits. Table 4-56 shows how the interface width for
the RX datapath is selected. 8B/10B decoding is described in more detail in RX 8B/10B
Decoder, page 228.
When the 8B/10B decoder is bypassed and the RX_DATA_WIDTH is 10, 20, or 40, the
RXDISPERR and RXCHARISK ports are used to extend the RXDATA port from 8 to 10 bits,
Table 4-56: FPGA RX Interface Datapath Configuration
RXDEC8B10BUSE RX_DATA_WIDTH FPGA Interface Width Internal Data Width
1
10 8 bits 20 bits
20 16 bits 20 bits
40 32 bits 20 bits
0
8 8 bits 16 bits
10 10 bits 20 bits
16 16 bits 16 bits
20 20 bits 20 bits
32 32 bits 16 bits
40 40 bits 20 bits
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English