110 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 2: Shared Transceiver Features
3. The total number of Quads sourced by an external clock pin pair
(MGTREFCLKN/MGTREFCLKP) must not exceed 3 Quads (or 12 GTX transceivers).
The maximum number of GTX transceivers that can be sourced by a single clock pin pair
is 12. Designs with more than 12 transceivers require the use of multiple external clock pins
to ensure that the rules for controlling jitter are followed. When multiple clock pins are
used, an external buffer can be used to drive them from the same oscillator.
Multiple External Reference Clocks Use Model
Each Quad has two dedicated differential reference clock inputs (MGTREFCLK0[P/N] or
MGTREFCLK1[P/N]) that can be connected to external clock sources. In the multiple
external reference clocks use model, each dedicated reference clock pin pair must
instantiate its corresponding IBUFDS_GTXE1 primitive to use these dedicated reference
clock resources. For details about placement constraints and restrictions on clocking
resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA
Clocking Resources User Guide. For the first external reference clock, the user design
connects the MGTREFCLK0[P/N] IBUFDS_GTXE1 output (O) to the MGTREFCLKRX[0]
and MGTREFCLKTX[0] ports of the GTXE1 primitive. For the second external reference
clock, the user design connects the MGTREFCLK1[P/N] IBUFDS_GTXE1 output (O) to the
MGTREFCLKRX[1] and MGTREFCLKTX[1] ports of the GTXE1 primitive. Even if the TX
PLL is not used, the corresponding reference clock ports that are used to drive the TX PLL
are still required to be connected to ensure the correct reset sequence of the GTX
transceiver. The TX reference clock ports can be tied to the clock driving the RX reference
clock ports.
Figure 2-6 shows two external reference clock sources connected to multiple GTX
transceivers within the same Quad.
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