Xilinx Virtex-6 FPGA User Manual

230 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Ports and Attributes
Table 4-38 defines the RX decoder ports.
Table 4-38: RX Decoder Ports
Port Dir Clock Domain Description
RXCHARISCOMMA[3:0] Out RXUSRCLK2 RXCHARISCOMMA indicates that the corresponding byte of
RXDATA is a comma character.
RXCHARISCOMMA[3] corresponds to RXDATA[31:24]
RXCHARISCOMMA[2] corresponds to RXDATA[23:16]
RXCHARISCOMMA[1] corresponds to RXDATA[15:8]
RXCHARISCOMMA[0] corresponds to RXDATA[7:0]
RXCHARISK[3:0] Out RXUSRCLK2 RXCHARISK indicates that the corresponding byte of RXDATA is a
K character when 8B/10B is used. These pins are reused as bit 8 of
each 10-bit word when 8B/10B is bypassed and the transceiver data
width is a multiple of 10.
RXCHARISK[3] corresponds to RXDATA[31:24]
RXCHARISK[2] corresponds to RXDATA[23:16]
RXCHARISK[1] corresponds to RXDATA[15:8]
RXCHARISK[0] corresponds to RXDATA[7:0]
RXDEC8B10BUSE In RXUSRCLK2 RXDEC8B10BUSE selects the use of the 8B/10B decoder in the RX
datapath, just after the comma detection/realignment block. If this
input is Low, the literal 10-bit data comes out as {RXDISPERR,
RXCHARISK, RXDATA<8 bits>}.
1: 8B/10B decoder enabled
0: 8B/10B decoder bypassed (reduces latency)
RXDISPERR[3:0] Out RXUSRCLK2 When High, RXDISPERR indicates that the corresponding byte of
RXDATA has a disparity error. These pins are reused as bit 9 of each
10-bit word when 8B/10B is bypassed and the transceiver data
width is a multiple of 10.
RXDISPERR[3] corresponds to RXDATA[31:24]
RXDISPERR[2] corresponds to RXDATA[23:16]
RXDISPERR[1] corresponds to RXDATA[15:8]
RXDISPERR[0] corresponds to RXDATA[7:0]
RXNOTINTABLE[3:0] Out RXUSRCLK2 RXNOTINTABLE indicates that the corresponding byte of
RXDATA was decoded from a 10-bit value that was not a valid
character in the 8B/10B table.
RXNOTINTABLE[3] corresponds to RXDATA[31:24]
RXNOTINTABLE[2] corresponds to RXDATA[23:16]
RXNOTINTABLE[1] corresponds to RXDATA[15:8]
RXNOTINTABLE[0] corresponds to RXDATA[7:0]
RXRUNDISP[3:0] Out RXUSRCLK2 RXRUNDISP shows the running disparity of the 8B/10B encoder
when RXDATA is received.
RXRUNDISP[3] corresponds to RXDATA[31:24]
RXRUNDISP[2] corresponds to RXDATA[23:16]
RXRUNDISP[1] corresponds to RXDATA[15:8]
RXRUNDISP[0] corresponds to RXDATA[7:0]
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English