Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 135
UG366 (v2.5) January 17, 2011
FPGA TX Interface
For details about placement constraints and restrictions on clocking resources (MMCM,
BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources
User Guide.
TXOUTCLK Driving More Than One GTX TX in 1-Byte Mode (Multiple
Lanes)
In Figure 3-7, TXOUTCLK is used to drive multiple GTX user clocks. In this situation, the
frequency must be correct for all the GTX transceivers, and they must share the same
reference clock. The example shows 1-byte mode (TX_DATA_WIDTH = 8 or 10), the
GEN_TXUSRCLK attribute is set to “FALSE”, and TXOUTCLK is used as the reference
clock for the MMCM.
TXOUTCLK is used to drive the CLKIN signal of the MMCM to derive two positive-edge
aligned CLKOUT0 and CLKOUT1 signals, where the CLKOUT1 frequency is equal to
CLKOUT0 frequency multiplied by 2. If the TX PLL for each transceiver is not used and
derived from the RX PLL, the active-High RXPLLLKDET signal should be used to deassert
the RST signal of the MMCM. TXOUTCLK can be used to drive CLKIN directly without
using the BUFG resources.
X-Ref Target - Figure 3-6
Figure 3-6: TXOUTCLK Driving More Than One GTX TX in 4-Byte Mode
GTX
Transceiver
TXPLLLKDET/
RXPLLLKDET
Design
in
FPGA
TXUSRCLK2
(1)
TXOUTCLK
RST
CLKIN
CLKOUT0
CLKOUT1
BUFG
BUFG
LOCKED
TXUSRCLK
(1)
MMCM
T XDATA (32 or 40 bits)
GTX
Transceiver
TXUSRCLK2
(1)
TXUSRCLK
(1)
T XDATA (32 or 40 bits)
Note 1: F
TXUSRCLK2
= F
TXUSRCLK
/2
UG366_c3_26_061609
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English