Xilinx Virtex-6 FPGA User Manual

264 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Link Idle Reset Support
The Link Idle Reset circuitry is built into the GTX receiver. The RX elastic buffer reset
sequence during an electrical idle condition is available for additional functionality.
During an electrical idle condition, the CDR circuit in the receiver can lose lock (see RX
CDR, page 204). To restart the CDR after an electrical idle condition, set the
RX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR, and RX_EN_IDLE_HOLD_CDR
attributes to TRUE. The CDR_PH_ADJ_TIME[4:0] attribute sets the wait time before
deassertion of the CDR phase reset and must be left at the default value.
The RX_EN_IDLE_RESET_BUF attribute enables a reset sequence for the GTX
transceiver’s RX elastic buffer. The RX elastic buffer of a GTX transceiver is automatically
held in reset and reinitialized after the end of an electrical idle condition on the RX pin pair
if the RX_EN_IDLE_RESET_BUF attribute is set to TRUE. The RX_IDLE_HI_CNT and
RX_IDLE_LO_CNT attributes control the timing of the RX elastic buffer reset sequence
and must be left at the default values.
GTX RX Component-Level Resets
GTX RX component resets are primarily used for special cases. These resets are needed
when only the reset of a specific subsection is required. Each component-level reset signal
is described in Table 4-54.
All receiver component resets are asynchronous with the exception of PRBSCNTRESET,
which is synchronous to RXUSRCLK2.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English