Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 147
UG366 (v2.5) January 17, 2011
TX Gearbox
Table 3-14 defines the TX gearbox attributes.
Enabling the TX Gearbox
To enable the TX gearbox for the GTX transceiver, the TXGEARBOX_USE attribute is set to
TRUE.
Bit 2 of the GEARBOX_ENDEC attribute must be set to 0 to enable the Gearbox decoder.
The decoder controls the GTX transceiver’s TX gearbox and RX gearbox. The GTX
transceiver’s TX gearbox and RX gearbox use the same mode.
TX Gearbox Bit and Byte Ordering
Figure 3-13 shows an example of the first five cycles of data entering and data exiting the
TX gearbox for 64B/66B encoding when using a two-byte logic interface. The input
consists of a 2-bit header and 16 bits of data. On the first cycle, the header and 14 bits of
data exit the TX gearbox. On the second cycle, the remaining two data bits from the
previous cycle's TXDATA input along with 14 data bits from the current TXDATA input
exit the TX gearbox. This continues for the third and fourth cycle. On the fifth cycle, the
output of the TX gearbox contains two remaining data bits from the first 66-bit block, the
Table 3-13: TX Gearbox Ports
Port Dir Clock Domain Description
TXGEARBOXREADY Out TXUSRCLK2 This output indicates if data can be applied to the 64/66 or 64/67
gearbox when GEARBOX_ENDEC is set to use the gearbox.
0: No data can be applied
1: Data must be applied
TXHEADER[2:0] In TXUSRCLK2 These ports are the header inputs. [1:0] are used for the 64/66 gearbox,
and [2:0] are used for the 64/67 gearbox.
TXSEQUENCE[6:0] In TXUSRCLK2 These inputs are used for the fabric sequence counter when the TX
gearbox is used. [5:0] are used for the 64/66 gearbox, and [6:0] are
used for the 64/67 gearbox.
TXSTARTSEQ In TXUSRCLK2 This input indicates the first word to be applied after reset for the
64/66 or 64/67 gearbox. The internal sequencer counter must be
enabled by the GEARBOX_ENDEC attribute.
Table 3-14: TX Gearbox Attributes
Attribute Type Description
GEARBOX_ENDEC 3-Bit Binary This attribute indicates the TX gearbox modes:
Bit 2: Always set to 0 to enable the gearbox decoder
Bit 1: The encoding for this bit is:
0: Use the external sequence counter and apply inputs to TXSEQUENCE
1: Use the internal sequence counter, gate the input header and data with the
TXGEARBOXREADY output
Bit 0: The encoding for this bit is:
0: 64B/67B Gearbox mode for Interlaken
1: 64B/66B Gearbox
TXGEARBOX_USE Boolean When TRUE, this attribute enables the TX gearbox.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English