Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 139
UG366 (v2.5) January 17, 2011
TX Initialization
GTX TX Reset in Response to Completion of Configuration
Figure 3-10 shows the GTX TX reset following the completion of configuration of a
powered-up GTX transceiver. The same sequence is activated any time
TXPLLPOWERDOWN goes from High to Low during normal operation.
Notes relevant to Figure 3-10:
1. GTXTEST[1] is only required when the TX output clock divider,
TXPLL_DIVSEL_OUT, is set to /2 or /4.
2. The timing of the reset sequencer inside the GTX TX depends on the frequency of an
internal clock and certain configuration attributes. The estimate given in Figure 3-10
assumes that the frequency of the internal clock is 50 MHz with default values for the
configuration attributes.
GTX TX Reset in Response to GTXTXRESET Pulse
Figure 3-11, similar to Figure 3-10, shows the reset occurring in response to a pulse on
GTXTXRESET. GTXTXRESET acts as an asynchronous reset signal. The guideline for the
asynchronous GTXTXRESET pulse width is one period of the reference clock.
X-Ref Target - Figure 3-10
Figure 3-10: Transmitter Reset After Configuration
GSR
TX Reset FSM
TXPLLLKDET/
RXPLLLKDET
TXRESETDONE
GTXTEST[1]
UG366_c3_28_092710
Wait
Reset in Progress
~120 µs
IDLE
1024
CLKs
256
CLKs
256
CLKs
256
CLKs
(1)
X-Ref Target - Figure 3-11
Figure 3-11: Transmitter Reset After GTXTXRESET Pulse
GTXTXRESET
TX Reset FSM
TXPLLLKDET/
RXPLLLKDET
TXRESETDONE
GTXTEST[1]
UG366_c3_29_092710
WaitIdle
Reset in Progress
~120 µs
Idle
1024
CLKs
256
CLKs
256
CLKs
256
CLKs
(1)
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English