Xilinx Virtex-6 FPGA User Manual

216 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Ports and Attributes
Table 4-31 defines the pattern checker ports.
Table 4-32 defines the pattern checker attributes.
Table 4-33 defines the RX pattern checker registers.
Use Models
To use the built-in PRBS checker, set RXENPRBSTST to match the PRBS pattern being sent
to the receiver. The RXENPRBSTST entry in Table 4-31 shows the available settings. When
the PRBS checker is running, it attempts to find the selected PRBS pattern in the incoming
Table 4-31: Pattern Checker Ports
Port Dir Clock Domain Description
PRBSCNTRESET In RXUSRCLK2 Reset PRBS error counter
RXENPRBSTST[2:0] In RXUSRCLK2 Receiver PRBS checker test pattern control. Only the following
settings are valid:
000: Standard operation mode (PRBS check is off)
001: PRBS-7
010: PRBS-15
011: PRBS-23
100: PRBS-31
No checking is done for non-PRBS patterns. Single bit errors
cause bursts of PRBS errors as the PRBS checker uses data from
the current cycle to generate next cycle’s expected data.
RXPRBSERR Out RXUSRCLK2 This non-sticky status output indicates that PRBS errors have
occurred.
Table 4-32: Pattern Checker Attributes
Attribute Type Description
RXPRBSERR_LOOPBACK 1-bit Binary This attribute can only be controlled via the DRP. The address location
for this attribute is bit 8 of 0x2A.
When this attribute is set to 1, the RXPRBSERR bit is internally looped
back to TXPRBSFORCEERR of the same GTX transceiver. This allows
synchronous and asynchronous jitter tolerance testing without
worrying about data clock domain crossing.
When this attribute is set to 0, TXPRBSFORCEERR is forced onto the
TX PRBS.
Table 4-33: Pattern Checker Registers (Read Only)
Attribute Type Description
RX_PRBS_ERR_CNT 16-bit Binary PRBS error counter. This counter can be reset by asserting
PRBSCNTRESET. When there is an error(s) in incoming parallel data,
this counter increments by 1 and counts up to 0xFFFF. This error
counter can only be accessed via the DRP. The address for this counter
is 0x82.
www.BDTIC.com/XILINX

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English