Xilinx Virtex-6 FPGA User Manual

266 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
After Power-up and Configuration
The entire GTX RX is reset automatically after the configuration-provided
RXPLLPOWERDOWN is Low. The supplies for the calibration resistor and calibration
resistor reference must be powered up before configuration to ensure correct calibration of
the termination impedance of all transceivers.
After Turning on a Reference Clock to RX PLL
The reference clock source(s) and the power to the GTX transceiver(s) must be available
before configuring the FPGA. The reference clock must be stable before configuration
especially when using PLL-based clock sources (e.g., voltage controlled crystal oscillators).
Table 4-55: Recommended Resets for Common Situations
Situation
Components to be
Reset
Recommended Reset
(1)
After power up and
configuration
Entire GTX RX After configuration, the GTX RX is reset automatically
After turning on a reference
clock to RX PLL
Entire GTX RX GTXRXRESET
After changing the reference
clock to RX PLL
Entire GTX RX GTXRXRESET
After assertion/deassertion
of RXPOWERDOWN
Entire GTX RX GTXRXRESET
RX rate change with RX
elastic buffer bypassed
RX PCS, RX Phase
Alignment
RXRESET
RX rate change with RX
elastic buffer enabled
RX PCS RX RESET
RX parallel clock source reset
RX PCS, RX Phase
Alignment
RXRESET
After remote power up RX CDR
A built-in reset sequencer automatically sets these situations by
setting RX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR,
RX_EN_IDLE_HOLD_CDR to TRUE
Electrical idle reset RX CDR
After connecting
RXN/RXP
(2)
RX CDR
After an RXBUFFER error RX Elastic Buffer RXBUFRESET
Before channel bonding
RX CDR, then
RXBUFFER after
CDR is locked
Either assert RXBUFRESET, or automatically reset by setting
RX_EN_IDLE_RESET_BUF = TRUE to enable the
RXBUFRESET sequence
After changing channel
bonding mode on the fly
RX Elastic Buffer
RX elastic buffer is reset automatically after change in channel
bonding mode by setting RX_EN_MODE_RESET_BUF to TRUE
After PRBS error PRBS Error Counter PRBSCNTRESET
After an oversampler error Oversampler RXRESET
After comma realignment
RX Elastic Buffer
(optional)
RX elastic buffer is reset automatically after comma realignment
by setting RX_EN_REALIGN_RESET_BUF to TRUE
Notes:
1. The recommended reset has the smallest impact on the other components of the GTX transceiver.
2. It is assumed that RXN/RXP are connected simultaneously.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English