Xilinx Virtex-6 FPGA User Manual

UG366 (v2.5) January 17, 2011 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Revision History
The following table shows the revision history for this document.
Date Version Revision
06/24/09 1.0 Initial Xilinx release.
08/11/09 2.0 Chapter 2:
• Added new sections: Using TXOUTCLK to Drive the GTX TX, page 131, GTX TX Reset in
Response to Completion of Configuration, page 139, GTX TX Reset in Response to
GTXTXRESET Pulse, page 139, GTX TX Component-Level Resets, page 140, After Power-
up and Configuration, page 142, After Turning on a Reference Clock to the TX PLL,
page 142, After Changing the Reference Clock to the TX PLL, page 142, After
Assertion/Deassertion of TXPOWERDOWN, page 142, TX Rate Change with the TX
Buffer Enabled, page 142, TX Rate Change with the TX Buffer Bypassed, page 142, TX
Parallel Clock Source Reset, page 142, TX Phase Alignment after Rate Change Use Mode,
page 159, and Rate Change Use Mode for PCI Express 2.0 Operation, page 171.
• Added the RXPLLREFSELDY[2:0] port to Table 2-4, page 106.
• Replaced first sentence of Single External Reference Clock Use Model, page 108.
• Added new section Multiple External Reference Clocks Use Model, page 110.
• Revised PLL nominal operating range and added Table 2-6, page 113.
• Added the PMA_COM_CFG attribute to Table 2-9, page 115.
•Replaced Table 2-10, page 117.
• Added PCI Express mode power conditions to bulleted list in Power-Down Features for
PCI Express Operation, page 123.
• Added note 1 to Table 2-10, page 117 on P1 and P2 power state support.
•In Dynamic Reconfiguration Port, page 125, revised occurrences of DO to DRPDO.
•In Table 2-18, page 126, changed the bus width of the DRP address bus to DADDR[7:0].
Chapter 3:
• Renamed TX Clock Divider Control block to TX Fabric Clock Output Control.
• Revised “GTX Lanes in Channel” values for 2-byte and 4-byte rows in Table 3-3, page 129.
• In the Functional Description of TX Initialization, page 136, revised #2 and added #3.
Added Figure 3-8, page 137 showing the GTX TX reset hierarchy.
• Revised the GTXTEST[12:0] and GTXTXRESET descriptions in Table 3-7, page 138.
• Revised Ease of Use and TX Lane-to-Lane Deskew rows in Table 3-15, page 153.
• Revised the TXDLYALIGNDISABLE, TXDLYALIGNMONITOR[7:0], and TXOUTCLK
descriptions in Table 3-18, page 155.
• Revised steps 2, 5, and 9 in Using t
he TX Phase-Alignment Circuit to Bypass the Buffer,
page 158.
• Changed the width of TXDLYALIGNRESET in Figure 3-21, page 159 to 16 TXUSRCLK2
cycles and revised caption.
• Revised paragraph under Figure 3-23, page 160 on making phase alignment effective.
•In Serial Clock Divider, page 168, provided more details on using the D divider in fixed
line rate and multiple line rate applications.
•In Table 3-28, page 168, removed TXPLL_DIVSEL_OUT = Ignored from all rows in the
Dynamic Control via Ports column.
•In Table 3-29, page 169, added the GTXTEST[1] port and revised the clock domain and
description of TXRATEDONE.
•In Table 3-30, page 170, revised the description of TRANS_TIME_RATE.
• Revised PCI Express Clocking Use Mode, page 170 and added Figure 3-29, page 171 and
Figure 3-30, page 172.
www.BDTIC.com/XILINX

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English