Xilinx Virtex-6 FPGA

162 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
TX Pattern Generator
Functional Description
Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of
high-speed links. These sequences appear random but have specific properties that can be
used to measure the quality of a link. The GTX transceiver pattern generator block can
generate several industry-standard PRBS patterns listed in Table 3-22.
In addition to PRBS patterns, the GTX transceiver supports 20 UI (or 16 UI) and 2 UI
square wave test patterns and PCI Express compliant pattern generation. Clocking pattern
is usually used to check PLL random jitter often done with a spectrum analyzer.
Error insertion function is supported to verify link connection and also for jitter tolerance
test. When inverted PRBS pattern is necessary, use TXPOLARITY signal to control polarity.
Table 3-22: Supported PRBS Pattern
Name Polynomial Length of Sequence Descriptions
PRBS-7 1 + X
6
+ X
7
2
7
– 1 bits Used to test channels with 8B/10B.
PRBS-15 1 + X
14
+ X
15
2
15
– 1 bits ITU-T Recommendation O.150, Section 5.3. PRBS-15 is often
used for jitter measurement as it is the longest pattern the
Agilent DCA-J sampling scope can handle.
PRBS-23 1 + X
18
+ X
23
2
23
– 1 bits ITU-T Recommendation O.150, Section 5.6. PRBS-23 is often
used for non-8B/10B encoding scheme. One of the
recommended test patterns in the SONET specification.
PRBS-31 1 + X
28
+ X
31
2
31
– 1 bits ITU-T Recommendation O.150, Section 5.8. PRBS-31 is often
used for non-8B/10B encoding scheme. A recommended PRBS
test pattern for 10 Gigabit Ethernet. See IEEE 802.3ae-2002.
Table 3-23: PCI Express Compliance Pattern
Symbol K28.5 D21.5 K28.5 D10.2
Disparity 0 1 1 0
Pattern 0011111010 1010101010 1100000101 0101010101
X-Ref Target - Figure 3-24
Figure 3-24: 20 UI Square Wave
UG366_c3_14_051509
20 UI
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