Xilinx Virtex-6 FPGA User Manual

160 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
Note: PHYSTATUS and USER_PHYSTATUS are used in PCI Express mode. USER_PHYSTATUS
is a gated version of PHYSTATUS from the GTX TX. It is recommended that PHYSTATUS indicating
a rate change completion is gated to the Media Access Layer (MAC) during TX phase alignment.
TXENPMAPHASEALIGN must remain asserted after a rate change.
Using the TX Phase Alignment Circuit to Minimize TX Lane-to-Lane Skew
The TX phase-alignment circuit can also be used to minimize skew between GTX
transceivers. Figure 3-23 shows how the phase-alignment circuit can reduce lane skew by
aligning the PMACLK domains of multiple GTX transceivers to a common clock.
Figure 3-23 shows multiple lanes running before and after phase alignment to a common
clock. Before phase alignment, all PMACLKs have an arbitrary phase difference, but after
alignment, the only phase difference is the skew for the common clock, and all data is
transmitted simultaneously as long as the datapath latency is matched.
X-Ref Target - Figure 3-22
Figure 3-22: TX Phase Alignment After Rate Change
TXRATEDONE
PHYSTAT US From GTX
GTXTEST[1]
16 TXUSRCLK2 Cycles
Required TXUSRCLK2 Cycles
TXENPMAPHASEALIGN
TXPMASETPHASE
TXRESET
TXRESETDONE
USER_PHYSTAT US or
SYNC_DONE to MAC
UG366_c3_30_122810
X-Ref Target - Figure 3-23
Figure 3-23: TX Phase Alignment Circuit to Reduce Lane Skew
Before
Phase Alignment
Parallel
Clocks Are
Independent
Skew
After
Phase Alignment
Parallel Clocks
Are Phase Aligned to
the Same Clock Edge
Reduced
Skew
GTX TX
GTX TXGTX TX
GTX TX
UG366_c3_12_051509
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English